CORTEX-M ARCHITECTURE BASICS

Training name

Cortex-M Architecture Basics

Level

Intermediate

Target Group

Firmware Developers on Cortex-M platforms (M0 to M7)

Prerequisites

Microcontroller Architecture concepts, Realtime/Embedded Programming concepts

Goals

Acquire basic Cortex-M Architecture knowledge

Facts

Duration: 1 Day – 8 hours
Maximum Number of Participants: 4 People

Content

This workshop is aimed at firmware developers for platforms based around the Cortex-M processors and includes an introduction to the Cortex Microcontroller Software Interface Standard (CMSIS) library.

The training covers the Arm Cortex-M0 to M7 core range, programmer's model and instruction set as well as the Cortex-M Coresight debug architecture.

Agenda

Cortex-M Architecture

Introduction

Cortex-M0

Cortex-M3

Overview, hardware characteristics, instruction set, bit banding
Privilege Levels
Execution Modes
Execution Stacks
Memory Map
Interrupt Handling
SysTick timer
MPU
Power Management

Cortex-M4

SIMD Instructions
Saturating Math
Floating Point Unit
DSP Library

Cortex-M7

Cache
Superscalarity
Coresight

CMSIS – Cortex-M Software Interface Standard
Hands - On Training

Blinking a LED on Nucleo-F401RE board using the SysTick Timer

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