The on-board firmware of the PLCcore-9263 contains the entire PLC runtime environment including CANopen connection with CANopen master functionality. Thus, the module is able to perform human-machine communication as well as control tasks such as linking in- and outputs or converting rule algorithms. Data and occurrences can be exchanged with other nodes (e.g. superior main controller, I/O slaves and so forth) via CANopen network, Ethernet (UDP protocol) and serial interfaces (UART). Moreover, the number of in- and outputs either is locally extendable or decentralized via CANopen devices. For this purpose, the CANopen-Chip is suitable. It has also been designed as insert-ready core module for the appliance in user-specific applications.
The PLCcore-9263 provides 16 digital inputs (DI0...DI15, 3.3V level), 8 digital outputs (DO0...DO7, 3.3V level) as well as Scroll Wheel and 4x4 Matrix Keypad support. This default I/O configuration can be adapted for specific application requirements by using the Driver Development Kit (SO- 1103).Saving the PLC program in the on-board Flash-Disk of the module allows an automatic restart in case of power breakdown.
Programming the PLCcore-9263 takes place according to IEC 61131-3 using the OpenPCS programming system of the company infoteam Software GmbH (http://www.infoteam.de). This programming system has been extended and adjusted for the PLCcore-9263 by the company SYS TEC electronic GmbH. Hence, it is possible to program the PLCcore-9263 graphically in KOP/FUB, AS and CFC or textually in AWL or ST. Downloading the PLC program onto the module takes place via Ethernet or CANopen – depending on the firmware that is used. Addressing in- and outputs and creating a process image follows the SYS TEC scheme for compact control units. Like all other SYS TEC controls, the PLCcore-9263 supports backward documentation of the PLC program as well as the debug functionality including watching and setting variables, single cycles, breakpoints and single steps.
The integrated target visualization of the PLCcore-9263 is based on the SpiderControl MicroBrowser of the company iniNet Solutions GmbH (http://www.spidercontrol.net). It allows both, the display of process values from the PLC and the forwarding of user actions to the PLC (eg input via touch screen, matrix keypad and scrollwheel).
The PLCcore-9263 is based on Embedded Linux as operating system. This allows for an execution of other user-specific programs while PLC firmware is running. If necessary, those other user-specific programs may interchange data with the PLC program via the process image.
- Caratteristiche e Benefici
PLCcore Firmware: IEC61131-3 runtime kernel pre-installed
Shared process image
CiA302/314 compliant CANopen manager
Customizable I/O driver
Program download via Ethernet or CANopen
Controller: Atmel® AT91SAM9G20,with ARM 926EJ-S Core,
System Clock: 440MIPS at 400MHz RAM: 32MiB SDR-SDRAM (64MiB optional) FLASH: 16MiB NOR (64MiB optional), 16-bit data-bus On-board Peripherals: DMA, MMU, hardware watchdog, temperature sensor, RTC Fast Ethernet: 1x 10/100Mbps, on-board PHY CAN: 1 UART: 4 USB: 2x USB 2.0 host, 12Mbps full-speed
1x USB 2.0 device, 12Mbps full-speed
SPI/I2C: 1 only with FPGA Firmware / 1 Mass storage: MMC/SD-card signals on board-to-board connector FPGA: Lattice ECP2-6 Others: SSC Operating Conditions: Temperature: -40°C…+85°C
Humidity: 10-90% RH, non-condensing
Power Supply: 3.3V +/- 5%, 1A max. Dimensions/Weight: 78 x 54 x 7,5 (L x W x H in mm) / 20g Board-to-board connector: 2x 50 pin header socket, 1.27 mm pitch Available on board-to-board connector: CAN, USB device, 2 USB host, I²C, 2 SD-card, Ethernet, 19 digital input lines, 8 digital output lines, 3 analog input lines, 4 PWM/DIO, 4 Timer/Counter/DIO RoHS compliant: yes Operating System: Linux Integrated Development Environment (IDE): Pre-integrated Eclipse-based IDE with GNU C/C++ tool chain, source- and assembly-level debugger, IEC 61131-3 IDE (OpenPCS) with SYS TEC vendor extensions Complementary Middleware: CANopen® Protocol Stack Source Code
Ethernet POWERLINK Protocol Stack Source Code